This invention relates generally to computer memory, and more particularly to providing synchronous dynamic random access memory (SDRAM) mode register shadowing in a memory system.
Contemporary high performance computing main memory systems are generally composed of one or more dynamic random access memory (DRAM) devices, which are connected to one or more processors via one or more memory control elements. Overall computer system performance is affected by each of the key elements of the computer structure, including the performance/structure of the processor(s), any memory cache(s), the input/output (I/O) subsystem(s), the efficiency of the memory control function(s), the main memory device(s), and the type and structure of the memory interconnect interface(s).
Extensive research and development efforts are invested by the industry, on an ongoing basis, to create improved and/or innovative solutions to maximizing overall system performance and density by improving the memory system/subsystem design and/or structure. High-availability systems present further challenges as related to overall system reliability due to customer expectations that new computer systems will markedly surpass existing systems in regard to mean-time-between-failure (MTBF), in addition to offering additional functions, increased performance, increased storage, lower operating costs, etc. Other frequent customer requirements further exacerbate the memory system design challenges, and include such items as ease of upgrade and reduced system environmental impact (such as space, power and cooling).
To achieve the wide range of performance, density and reliability objectives, as well as to achieve aggressive time-to-market goals in the competitive systems market, developers often add features and/or “hooks” to facilitate fault diagnosis during system bring-up and characterization. Ideally, any added features will offer benefits both prior to and after systems are introduced to the marketplace, including such benefits as enhanced/rapid fault diagnosis, reduced power-up time, simplified operational adjustments to varying environmental conditions, etc.
FIG. 1 relates to U.S. Pat. No. 5,513,135 to Dell et al., of common assignment herewith, and depicts an early synchronous memory module. The memory module depicted in FIG. 1 is a dual in-line memory module (DIMM). This module is composed of synchronous DRAMs 8, buffer devices 12, an optimized pinout, and an interconnect and capacitive decoupling method to facilitate high performance operation. The patent also describes the use of clock re-drive on the module, using such devices as phase-locked loops (PLLs).
FIG. 2 relates to U.S. Pat. No. 6,173,382 to Dell et al., of common assignment herewith, and depicts a computer system 10 which includes a synchronous memory module 220 that is directly (i.e. point-to-point) connected to a memory controller 14 via a bus 240, and which further includes logic circuitry 24 (such as all application specific integrated circuit, or “ASIC”) that buffers, registers or otherwise acts on the address, data and control information that is received from the memory controller 14. The memory module 220 can be programmed to operate in a plurality of selectable or programmable modes by way of an independent bus, such as an inter-integrated circuit (I2C) control bus 34, either as part of the memory initialization process or during normal operation. When utilized in applications requiring more than a single memory module connected directly to a memory controller, the patent notes that the resulting stubs can be minimized through the use of field-effect transistor (FET) switches to electrically disconnect modules from the bus.
Relative to U.S. Pat. No. 5,513,135, U.S. Pat. No. 6,173,382 further demonstrates the capability of integrating all of the defined functions (address, command, data, presence detect, etc) into a single device. The integration of functions is a common industry practice that is enabled by technology improvements and, in this case, enables additional module density and/or functionality.
FIG. 3, from U.S. Pat. No. 6,587,912 to Bonella, et al., depicts a synchronous memory module 210 and system structure in which the repeater hubs 320 include local re-drive of the address, command and data to the local memory devices 301 and 302 via buses 321 and 322; generation of a local clock (as described in other figures and the patent text); and the re-driving of the appropriate memory interface signals to the next module or component in the system via bus 300.
FIG. 4 depicts a contemporary system composed of an integrated processor chip 400, which contains one or more processor elements and an integrated memory controller 410. In the configuration depicted in FIG. 4, multiple independent cascade interconnected memory interface busses 406 are logically aggregated together to operate in unison to support a single independent access request at a higher bandwidth with data and error detection/correction information distributed or “striped” across the parallel busses and associated devices. The memory controller 410 attaches to four narrow/high speed point-to-point memory busses 406, with each bus 406 connecting one of the several unique memory controller interface channels to a cascade interconnect memory subsystem 403 (or memory module) which includes at least a hub device 404 and one or more memory devices 409. Some systems further enable operations when a subset of the memory busses 406 are populated with memory subsystems 403. In this case, the one or more populated memory busses 406 may operate in unison to support a single access request.
FIG. 5 depicts a memory stricture with cascaded memory modules 503 and unidirectional busses 506. One of the functions provided by the hub devices 504 in the memory modules 503 in the cascade structure is a re-drive function to send signals on the unidirectional busses 506 to other memory modules 503 or to the memory controller 510. FIG. 5 includes the memory controller 510 and four memory modules 503, on each of two memory busses 506 (a downstream memory bus with 24 wires and an upstream memory bus with 25 wires), connected to the memory controller 510 in either a direct or cascaded manner. The memory module 503 next to the memory controller 510 is connected to the memory controller 510 in a direct manner. The other memory modules 503 are connected to the memory controller 510 in a cascaded manner. Although not shown in this figure, the memory controller 510 may be integrated into a processor and may connect to more than one memory bus as depicted in FIG. 4.
In a memory subsystem, a memory interface device (MID) (e.g., for providing an interface between a memory controller and SDRAM devices) will have sections of its logic that need to be configured to match the programming of the SDRAM device(s) mode register settings (this is referred to as the MID's SDRAM-dependent configuration). There is some overall inefficiency, as well as potential for error if this configuration needs to get programmed twice: once for the SDRAM via mode register set commands, and then again for the MID. Additionally, since the SDRAM mode register contents can not be read back, any memory subsystem failure due to unmatched configuration between the MID and a SDRAM can be difficult to diagnose. This difficulty increases with the number of ranks of SDRAM devices that the MID controls.
Whereas initial synchronous memory devices included only a single mode register, with limited programmable functions/attributes, emerging SDRAMs (such as DDR3 and DDR4) include four or more mode registers (e.g. MR0 through MR3) that correspond to extensive programmable memory device features affecting functionality, performance, drive characteristics, I/O terminations, power dissipation, refresh, temperature sensing, etc. The increase in mode register size and complexity, in conjunction with the current need to program all memory devices as well as MIDs in the system, results in increased system debug time (initial system evaluation, analysis and/or test escapes (e.g. all possible combinations may not be tested and/or may not be testable at the time of system shipment)) and a significant startup time increase.
It would be desirable to provide an efficient process for allowing MIDs to monitor the programming of SDRAM mode registers. Ideally this process would include having the same mode register set command(s) and associated configuration data being applied to both the MID and the SDRAM registers.